PIC16C711-20/SO【PDF 84/177 页】IC MCU OTP 1KX14 A/D 18SOIC

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Sheet目录3861

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174

7593L–AVR–09/12

AT90USB64/128

Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low

when idle. Refer to Figure 18-3 and Figure 18-4 for an example. The CPOL functionality is sum-

marized in Table 18-2:

Bit 2 – CPHA: Clock Phase

The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or

trailing (last) edge of SCK. Refer to Figure 18-3 and Figure 18-4 for an example. The CPOL

functionality is summarized Table 18-3:

Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have

no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f

osc is

shown in Table 18-4:

18.1.4

SPSR – SPI Status Register

Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in

SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is

in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the

Table 18-2.

CPOL functionality.

CPOL

Leading edge

Trailing edge

Rising

Falling

Rising

Table 18-3.

CPHA functionality.

CPHA

Leading edge

Trailing edge

Sample

Setup

Sample

Table 18-4.

Relationship between SCK and the oscillator frequency.

SPI2X

SPR1

SPR0

SCK frequency

osc/4

osc/16

osc/64

osc/128

osc/2

osc/8

osc/32

osc/64

Bit

SPIF

WCOL

–

SPI2X

SPSR

Read/write

RR/W

Initial value

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